The present invention relates to error correction for flash memory.
Continuous improvements in price/performance for flash electrically-erasable programmable read-only memory have enabled flash memory to become the long term storage of choice for many applications. A flash memory is typically made from an array of floating-gate metal-oxide-silicon field effect transistors arranged as memory cells in typical row and column fashion with circuitry for accessing individual cells and placing the memory transistors of those cells in different memory conditions. Such memory transistors may be programmed by storing a charge on the floating gate. This charge remains when power is removed from the array. This charge (a “zero” or programmed condition) or its absence (a “one” or erased condition) may be detected when the device is read. Flash memory arrays are especially useful in portable computers where low power consumption is mandatory, space is at a premium and weight is important.
Two common flash memory architectures are NAND-type structure (NAND-flash) and NOR-type structure (NOR-flash). The NAND-flash serially arranges its memory cells while the NOR-flash arranges memory cells in parallel. An advantage of the NAND-type structure is faster sequential accessing than the NOR-type structure. In addition, the NAND-type structure supports faster write and erase operations and permits fabrication of higher density memory chips or smaller and less expensive chips of the same density.
During fabrication, flash memory devices may contain defective areas, and more defects may appear during the device lifetime, thereby limiting their usage. To manage these defects and to achieve efficient and reliable operation, digital systems typically use techniques to control errors and to ensure reliable data reproduction. For example, if hardware error occurs in a block of the array, that block of the array can be removed from operation. Blocks of flash memory are relatively expensive compared to other forms of storage, so this technique of having redundant/spare storage blocks is undesirable. Moreover, since only a limited number of spare blocks of flash memory are available in an array, this error correction approach eventually restricts the ability of the device to function.
A typical device (for example a Samsung K9F1208U0M 64M×8 flash memory) includes 16 extra bytes per 512-byte page. Manufacturers typically recommend error protection capability to detect 2-bit errors or to correct single bit errors on each device page (4096 bits). NAND-flash devices typically ship with an additional 16-byte area for each 512-byte page, for a total of 528 bytes. Some NAND-flash manufacturers rely on external ECC in order to support an extended number of write cycles per page/block. In the past, certain standards for NAND-flash file systems have been set, which include limited data protection. One such standard is the SmartMedia™ standard, mainly targeted for removable flash memory cards. This standard includes single-bit error correcting code that can also detect (but not correct) 2-bit errors per 256 bytes. The SmartMedia™ standard allocates 6 bytes for ECC related information per page. In addition, 2 bytes are used to duplicate logical block address information already included elsewhere. Therefore, a total of 8 bytes are allocated for this information. The SmartMedia™ standard sets aside bytes 0-511 for data storage and the following as an extra storage area: byte 516 for data status, byte 517 for block status, bytes 518-519 for block address field 1, bytes 520-522 for ECC field 2, bytes 523-524 for block address field 2, and bytes 525-527 for ECC field 1. The SmartMedia™ standard proposes the use of a Hamming-like code using 6 parity bytes (actually 22×2 bits). This code is capable of detecting up 2-bit errors and of correcting a single bit error per 256 bytes. However, the SmartMedia™ specification does not provide error detection and correction for the extra storage area.
U.S. Pat. No. 6,438,706 to Brown entitled “On Chip Error Correction For Devices In A Solid State Drive” provides an error correction arrangement for a flash memory with a plurality of redundant array circuits, a circuit for sensing when a hardware error has occurred in a block of the flash array, and a circuit for replacing an array circuit with a redundant array circuit in response to detection of a hardware error. However, this approach does not correct for one, two or three bits of errors.
As high-speed digital systems employing flash memory become more widely used and integral to day-to-day activities, individuals likely will depend more upon the efficient and reliable reproduction of the data stored in the flash memory of these digital systems.